In an SSC, as indicated by (A) in FIG. 9, a pseudo noise code (hereinbelow abbreviated to PN code) is modulated by data and a carrier signal is modulated by the modulated PN code to be transmitted.
In (A) in FIG. 9, reference numeral 1 represents the data; 2 is a modulator; 3 is a PN code generator; 4 is a carrier signal generator; 5 is a modulator; and 6 is an antenna.
On the receiver side, as indicated by (B) in FIG. 9, the signal is received and correlated with a PN code serving as a reference by a correlator. A self-correlation spike waveform having a relatively great amplitude appearing when the signal described previously and the code are in accordance with each other and when they are close to each other is processed for reproducing data.
In (B) in FIG. 9, reference numeral 7 is an antenna; 8 is a correlator; 9 is a reference PN code generator; 10 is a data demodulator; and 11 represents the data.
As an example of the correlator described above there is known a digital correlator. FIG. 10 shows a basic circuit construction of the digital correlator. In the figure, S and R are shift registers; Ex-NOR.sub.1 to Ex-NOR.sub.1 are NOR gates; and ADD is an adder. Reference data REF of N bits are inputted serially to the shift register R of N bits in synchronism with a clock RCLK. On the other hand, information data DATA are inputted serially to the register S of N bits in synchronism with a clock SCLK. Accordance and disaccordance of the contents of the registers are detected by the NOR gates for every bit and the total number of bits, which are in accordance with each other, is obtained by the adder ADD.
FIG. 11 shows one of constructions, in the case where the digital correlator as indicated in FIG. 10 is applied to the SSC. In the FIG. 1 and 2 are multipliers; 3 and 4 are low pass filters (LPF); 5 and 6 are A/D converters; 7 and 8 are digital correlators; and 9 is an adder. FIG. 12 is a diagram for explaining the data demodulation at receiving an SS signal (hereinbelow abbreviated to SS-BPSK) modulated by the bi-phase shift keying (hereinbelow abbreviated to BPSK).
Now asynchronous demodulation operation for the SS-BPSK signal according to FIG. 11 will be explained. The SS-BPSK signal can be expressed by Equation (1); EQU r(t)={f(t).sym.PN(t)}.COS.omega.ot (1)
f(t): digital data corresponding to "1" or "0" PA1 PN(t): PN code (Pseudo Noise Code) PA1 .sym.: exclusive or PA1 COS.omega.ot modulation carrier signal
In FIG. 11, as indicated in FIG. 12, a COS component and a SIN component are obtained by multiplying the SS-BPSK signal by COS.omega.t and SIN.omega.t having a same frequency as a modulation carrier frequency for the SS-BPSK signal by means of the multiplier 1 and 2, respectively. PN code chips are extracted from the components by the low pass filters LPF 3 and 4 having a cut-off frequency, which is equal to the PN code clock frequency. The data modulation is effected by effecting the base band processing by means of the digital correlators 7 and 8, after they have been A/D-converted by means of the A/D converters 5 and 6, respectively.
That is, correlation values of the digital data of the COS component and the SIN component are obtained by means of the digital correlators 7 and 8, for which reference data, which are equal to a result of the exclusive logic sum of e.g. data "1" at the transmission and the PN code, are set. Then the data demodulation is effected on the basis of the value obtained by adding the different correlation values by means of the adder 9.
However the prior art digital correlating device described above has a problem as follows.
That is, when PN code chip waveforms obtained by the low pass filters LPF 5 and 6 indicated in FIG. 11 are A/D-converted, it is desirable to sample ideally a point P, at which the level of the PN code chip waveforms is most stable, with an interval, which is equal to the PN code clock period, as indicated in FIG. 13. However, it is difficult to sample the point P in FIG. 13 by the asynchronous SS-BPSK demodulating method as indicated in FIG. 11. As a measure taking the place thereof, there is known usually a method, by which the sampling frequency is raised. However, by this method, since the amount of information corresponding to one PN code chip increases with increasing sampling frequency, it is necessary to increase the number of stages of the shift registers in the digital correlators.
For example, in the case indicated by (B) in FIG. 13, the sampling period T is reduced to 1/4 of that indicated by (A) in FIG. 13. Therefore the number of stages of the shift registers in the digital correlators should be increased by a factor of 4.